It's my understanding that Modelio is implemented primarily in C++, and Eclipse, primarily in Java. MOF and UML effectively extend on XML Schema Datatypes (XSD) so it's not an innately language-centric framework, however. Of course, insofar as how XMI is applied within specific modeling platforms,, there are broad differences between platform vendors' own implementations of the standard. However, pretty much all of it is encoded in XML, and encoded according to a normative model serialization methodology, in each respective modeling tool vendor platform. Certainly, some vendors have focused a lot on code generation -- Modelio can even do "Round trip" analysis on Java class file definitions. The "XMI part," however, might seem to be pretty much ad hoc, per each vendor's implementation, but nonetheless it's all information structured in XML.
My now gaining some simple practical experience with regards to electronics design automation (EDA) tools -- such a Altera Quartus II Web Edition -- as a student of DeVry University Online, moreover in endeavoring to "Look ahead" towards developing any single thesis concept for the inevitable "Senior project," for a deadline sometime down the proverbial road of academic progress, and as being presently in a week's break between a semester's two sessions with DVUO, I've been taking some time to compile some more research resources, and to sketch out some simple notes for possible software and electronics design projects for "the months ahead," before I'll have completed the initial associates degree. Sure, I am "that much of an undergrad," formally.
While conducting some such focused research, last night, I'd noticed that a few JEDEC standards were referenced from the Altera Cyclone III Device Handbook (p. 6-12 / PDF p. 110) -- that there are a select number of JEDEC JESD standards referenced, there, as in regards to compatibility onto standards for CMOS/LVCMOS, TTL/LVTTL, and PCI voltage ratings. As a student of DVUO's ECT programs, personally I now own an eSOC3 board with a Cyclone III FPGA device installed on the same. Sure, the board doesn't have any design documents available for it, so I might not be able to make any use of the thing, now that the initial ECT-114 class is complete. At least, there might be some proverbial "Mileage" in the actual manual for the FPGA device, itself. (Maybe sometime, I could simply desolder the thing and put into a normal proto-board. To return to the present matter, however...)
After further searching online, this afternoon -- namely, having searched the dynamic, "world wide virtual library" to learn if there would be something in regards to standards for functionally individual logic gates, such that could serve as a normative, vendor-neutral reference, towards developing a sort of object-oriented hardware definition model for modeling digital logic systems in Common Lisp -- I'd found, specifically, JEDEC JESD 75-5, ON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS. I think it's quite a nice little reference manual, the same, though I've noticed now that it's a specification specifically about integrated circuits packaged in QFN format and other Small Outline (SO) formats. I'd noticed the item, firstly, in that it provides a nice, enumerated list of standard logical functions in manufactured integrated circuits, such as the dual input digital AND gate, some couple of types of digital logic inverter, and the inevitable "D Flip-Flop" (DFF)
Focusing on the matter of the enumerated set of logical functions, in that document: Certainly, JESD 75-5 does not, itself, define the exact functional behaviors of those standard circuit elements (AND, NOT, and the DFFs) -- such as would be indicated in a truth table for each, such that, of course, one might find in most manufacturer's data sheets. Inasmuch, JESD 75-5, itself, does not specify any exact, practical applications for those circuit elements. However, I think it's helpful that they at least have assigned some standard nomenclature to the same logical circuit functions enumerated in the document -- at least in their QFN and SON packaging (?) -- including AND, DFF, and inverter circuits. If perhaps it could also serve in making a simple, enumerated list of those logical functions thusly standardized, then personally I think it could be of interest towards defining a vendor-neutral schematic model.
I think, the set of JEDEC documents is certainly nicer to see than an old edition of MIL-STD 1562 (not classified), as far as standardization in digital electronics.
So, evidently there are vendor-agnostic standards for those digital logic "things". I think that's reassuring. However, noticing that JESD 75-5 refers to digital circuit elements manufactured specifically in QFN or SON packaging -- with definitions in the document, describing the characteristics of the same -- perhaps such a foremost reference as I was looking for.
It seems that the effective, contemporary "roots" of the JEDEC digital electronics standardization tree -- so to speak -- would be defined in JEDEC JEP95, across a number of categories such as for standard qualities of diodes, transistors, and microelectronics. I'm sure it might not seem so interesting, however, if outside of the possibility of defining a software meta-model for an effective, standardized representation of those same qualities as standardized in JEDEC '95 -- a meta-model as in reference to OMG SysML, UML, and MOF -- towards defining a vendor-neutral EDA platform, moreover, ideally extending on existing free/open source software components.
JEP95 defines, in the JEP95 Microelectronics Outline (MO) Device Type (DT) index, a broad index of standard categories for integrated circuit packaging, like in a sense of socket formats -- not the carrier packaging apparently the topic of the CO and CS indexes in JEP95 -- rather, the socket packaging of circuits as would be installed onto a printed circuit board (PCB). Some of the items in that index may seem "outdated" -- such as the Quad In-Line (QUIP) socket format -- an IC socket format that was used, "once upon a time," in some Intel components in the iAPX 432 midromainframe (circa 1981). However, if technology may be regarded more as a function of science and engineering, without too much of an emphasis on "treandiness," the term "Outdated" would not seem to have much of a sense of relevance, in the simply technical view.
So, in reading the JEP95 MO//DT index as an index of socket formats, it may serve to inform a model for application in computer aided design and drafting (CADD) in electronic design automation (EDA). However, in itself, JEP95 does not define any of the functional qualities of integrated circuits.
JEP95 is referenced from JESD 75-5. Perhaps there may be something similar to JESD 75-5 but more specifically about DIP and SMD formats for TTL and CMOS circuit elements? I should update my notes, here, sometime after researching that matter, further.
Notably, in furthermore:
- JEDEC also publishes a nice, formal dictionary of technical terms: JESD 88
- JESD 30F - Descriptive Designation System for Semiconductor-Device Packages, none closer to a functional description but of more interest for the definition of a generic, vendor-neutral digital circuit component metamodel, for application within a digital circuit design environment. JESD30F is another JEDEC JC-10 specification
- JESD 75-4, contextually similar to JESD 75-5 but defined about BGA packaging
- JEDEC JC-40, Digital Logic, JEDEC Committee
- The BGA-focused JESD 75-<N> standards, as published under JC-40, might serve to define something of a normative reference base, towards a baseline digital logic model, in bit ranges of 1, 2, 3, 8, 16, 18, 20 and 32 bits.
- Logic Cross-Reference from Texas Instruments (313 pp. PDF) focused on individual integrated circuit types
- Selection and Solution Guides, an index of reference resources
- The Little Logic Guide (25 pp. PDF)
- Terminology (pp. 5-6)
- CBT: Bus Switch
- CBTLV: Low-Voltage Bus Switch
- CB3T: Low-Voltage Translation Bus Switch
- LVC: Low-Voltage CMOS (1.65 V to 5.5V, or 1.8V to 5.5V depending on product range)
- AUC: Advanced Ultra-Low-Voltage CMOS
- AUP: Advanced Ultra-Low-Power CMOS
- Indexes:
- Single-gate logic functions, pp. 9-11. "G" numbers corresponding to JESD 75-4 (e.g 1G00, 1G02) with some omissions (e.g 1G05) and some additions (e.g 1GX04 Crystal Oscillator Driver)
- Dual-gate logic functions, pp. 12-13
- Triple-gate functions, p. 14
- Single-switch functions, p. 14
- Configurable functions, p. 15
- Voltage translation functions (single-supply and dual-supply), pp. 15-16
- LVC devices (competitor xref) pp. 17-19
- AUC devices (competitor xref) p. 19
- Signal-switch devices (competitor xref), p. 20
- AUP devices (competitor xref), pp 20-21
- low power logic functions. see Logic Guide p. 15
- AHC and AHCT devices (competitor xref), p. 21
- Configurable devices and AUP1T translators, p. 22
- The Logic Guide (125 pp. PDF)
- AUP devices, p. 15
- low power logic functions
- mobile device applications
- GTLP and VME devices, p. 29
- Optimal backplanes
- I2C, PCI, ...
- Product index begins at p. 31
- Hamilton, William. Lectures on metaphysics and logic. ed. Henry Mansel, and John Veitch. W. Blackwood and Sons (Edinburgh). 1874
- Notably, no references to Boole or De Morgan
- Syllogisms, philosophical logic
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