Showing posts with label Verilog. Show all posts
Showing posts with label Verilog. Show all posts

Friday, November 14, 2014

A Short Overrview Towards EDA Tool Selections: Schematic Capture and FPGA Development

As the author being an aspiring student of mathematics and electrical engineering -- presently, studying formally in a series of sort of introductory courses affiliated with the latter discipline, electrical engineering -- the author has had something of an opportunity to develop a sense of familiarity, mostly informally, with regards to a small number of software tools such that might be denoted as Electronic Design Automation (EDA) platforms.

In the college that the author is formally a student to, the Multisim platform -- as developed by National Instruments -- is the schematic capture program that the courses apply, specifically for any laboratory assignments including a circuit schematic and not implemented in regards to introductory FPGA programming. For FPGA programming, namely as in the introductory digital logic course, the FPGA platform in use is Altera's Quartus II Web Edition.

The author not being a veteran electrical engineer, this short comment will not be accompanied with any manner of salesmanship about those specific EDA platforms. Multisim certainly presents a fairly straightforward GUI, with a simple interface for circuit simulation. Multisim implements VHDL and Verilog. Quartus II, then, is certainly one of the the available platforms for programming Altera FPGAs. Altera's Cyclone III FPGA is applied in one eSOC board, such that is used, albeit exclusively, in the single introductory digital logic course at the college. Perhaps the eSOC board might present a challenge for circuit analysis, at some time, as it's not accompanied with any sort of schematic or other design files, in its current edition.

Certainly -- regarding those specific EDA tools -- though those would be applied of any single college or university, but certainly, those may not represent the only EDA tools in the known universe.

Onto Schematic Capture and Circuit Analysis


As alternate to Multisim, there's Cadence's OrCAD Capture. OrCAD supports the Verilog and VHDL formats, OrCAD, moreover, provides support for projects applying the EDIF format, such as is latterly subsumed of ISO 10303 and the STEP model. There being a few editions of the complete OrCAD EDA platform, OrCAD Lite is the free edition -- certainly, in some features, extending free/open source software, such as the GNU Compiler Collection (GCC). Insofar as OrCAD licensing, there is -- in fact -- an educational licensing model available from Cadence, for licensing of the OrCAD platform.

For those of us whom might be approaching OrCAD as student or hobbyist, perhaps also for those whom might be approaching OrCAD as, each, an aspiring electrical engineer, Cadence publishes a wealth of documentation about the OrCAD platform, broadly:

Personally, the author became aware simply of the existence of the OrCAD platform, courtesy of Edward Brumgnach's book, i.e [Brumgnach2014] Cadence OrCAD Capture Version 16, a Primer: Circuit Analysis, Electronics, and Digital, Kindle edition. The introduction presented in [Brumgnach2014] is certainly nothing intimidating, providing an overview of the OrCAD Capture graphical user interface and a number of the fundamental features of OrCAD Capture -- such as for circuit component placement, circuit simulation, and quantitative circuit analysis using OrCAD -- all addressed in a context of DC analog circuitry. The introduction, as such, is conveyed as in parallel to a short survey of fundamental principles of the electrical sciences, focusing mainly on Ohm's Law, as likewise in regards to DC analog circuitry. A study of the significance of electrical impedance -- as with regards to a current of a varying polarity, as within a circuit of a resistive element and one or more of each of a dielectric capacitive element and an inductive element -- such a study might be left as an exercise for the reader.

Notably, perhaps, the schematics components of the design files for the BeagleBone Black platform are published in DSN format, a format supported by by OrCAD Capture.



Onto the Papilio FPGA Platform

In addition to OrCAD, specifically as with regards to FPGA projects, this web-log cordially recommends Xilinx FPGAs. In regards to evaluation boards for FPGA programming, if not also in regards to environments for study and for prototyping, Xilinx Spartan FPGAs, namely, are applied in the Papilio platform -- respectively, a Spartan 3E FPGA in Papilio One, and a Spartan 6 FPGA in Papilio Duo. For programming the Papilio platform, the ZAP IDE is available, as extending of some functionality provided specifically in Xilinx ISE Web Pack.  ISE WebPack is likewise available with a free license, as a feature of the Xilinx ISE Design Suite.

Linux may be a recommended operating system platform for applying ISE Web Pack's tools. This web-log recommends the Kubuntu Linux distribution. Linux can be installed simultaneous to a Microsoft Windows operating system, either with a dual-boot configuration, or in a virtualization platform installed to the Microsoft Windows OS -- at which, this web log recommends Virtualbox for a single-user desktop environment, and Xen  as for enterprise-scale virtualization scenarios in so much of software defined networking (SDN).

Xilinx publishes a wealth of documentation, likewise -- such as about Xilinx' Spartan FPGA products and the ISE Design Suite tools as licensed under the ISE WebPack platform and as available under other licenses for Xilinx ISE Design Suite -- for example, Tutorials about Xilinux ISE Design Suite, and User Guides as with regards to the same design platform. For applications of the ISE Web Pack tools on Linux platforms, some additional documentation is available of the Arch Linux Wiki. Certainly, in installing even so much as the Xilinux ISE WebPack edition of the ISE Design Suite platform, a broad range of features are then made available, within the containing operating system.

An introduction to digital logic, as well as the VHDL hardware definition language and FPGA programming, is available in PDF and in ASCIIDOC formats [web][github]. For general prototyping with the Papilio platform, this web log recommends the ZPUino soft processor for the Papilio FPGA platform. The Papilio board -- such as Papilio One or Papilio Duo -- when programmed with the ZPUino soft processor -- may be programmed in applications of a syntax similar to the Arduino sketch file format [Arduino] though namely in using the ZAP IDE.

Towards programming a Papilio FPGA board with the ZPUino soft processor  and then developing an initial sketch file in the ZAP IDE,  Gadget Factory publishes a convenient getting started tutorial, addressing both matters. The tutorial introduces the overall working process for programming Papilio with a soft processor -- there, using the Xilinux ISE tool and the Papilio schematic library, as published by Gadget Factory, to the matter of uploading a bit file to the FPGA board, effectively thereby installing ZPUino to the Papilio board -- followed, then, with an introduction towards programming the ZPUino soft processor with a sketch file in Zap IDE,

Towards MBSE modeling for FPGA Environments

Certainly, FPGA programming represents a broad subdomain of electrical engineering. Towards a matter of model-based systems engineering (MBSE) perhaps towards developing a sort of macro-level, object-focused analysis towards an FPGA system, this article directs the reader's attention towards the ENOSYS Tool set for FPGA systems synthesis. as published courtesy of Softeam. The ENOSYS tool set develops something of a unique view about FPGA systems programming, effectively extending the Object Management Group (OMG) specifications for the Unified Modeling Language (UML) extended then into an EDA domain. The ENOSYS toolchain effectively presents an interface onto bare metal hardware, at Falcon ML,

Towards a singular overview about the Unified Modeling Language (UML), as well as the Systems Modeling Language (SysML) and the MetaObject Facility (MOF) -- of which, in extending of the MOF meta-metamodel, as defined by the OMG, the specifications of UML and SysML are implemented, literally, as metamodels -- the  reader's attention is directed to a book published by Morgan Kaufmann in affiliation with the Object Management Group, a book by Tim Weilkeins, Systems Engineering with SysML/UML: Modeling, Analysis, Design

Disambiguation: This article does not address the ENOSYS error code, as defined in contemporary C toolchains, "Function not implemented".


Segue to "Fin," Towards Theory and Praxis

In the foundry text, PhilosophiƦ Naturalis Principia Mathematica, Isaac Newton develops a concept of a juxtaposition of geometric and mechanical views with regards to mechanical systems. Such a juxtaposition may be understood as being reified, effectively, in electrical engineering -- analogously, as with regards to models for circuits, and of physical circuits, in situ. Certainly, the history of circuit modeling extends at least so far back as to the original development of Ohm's Law, previous to so many developments in analog and digital electrical systems, and -- then furthermore -- to the origins of the contemporary Euclidean geometry.

Towards developing a sense of knowledge with regards to practical applications of mathematics and the electrical sciences, certainly resources abound, as in collections of formal, public libraries and online. Towards online resources, as with regards to theories developed in and of the electrical sciences, this article cordially recommends: Hyperphysics -- a resource published online, by the Department of Physics and Astronomy at Georgia State University.

With regards to studies of practical applications for the electrical sciences, this article recommends the online resources published by each of:

Thursday, May 29, 2014

Modeling the LispM – Quartus II and CADR, an Outline

Ed. Note: This article should subsequently be updated for modeling of the CADR schematic, using Xilinux ISE Web Pack, and the Papilio FPGA platform -- ideally, then to develop an I2C bus as initial extension onto the original CADR design, such that the I2C bus could be operated via the GPIO headers on the Papilio platform, in communicating with one or more other devices on the same I2C backplane. See also: TI PRU Cape for the BeagleBone platform.

CADR

  • Lisp Machine
  • Developed at MIT (circa late 1970's, early 1980's)
  • Predecessor machine was CONS
  • Described in public domain (?) AI Memos originally published by the MIT AI Lab
    • Design
    • Schematics
    • Wiring/Pinouts
    • Peripherals incl. Chaosnet network interface
  • Designed in an era when integrated circuit (IC) technology was implemented primarily in applying techniques of transistor-transistor logic (TTL)
    • ICs composed of circuits of bijunction transistors, resistors, capacitors, packaged in multiple elements within individual integrated circuit modules (e.g four SEL-D FF elements to one 25S09 IC)
    • Standard (?) TTL logic/voltage bounds
      • high/lowmin/max voltage ranges on each of TTL circuit element input and output
      • "Nondeterministic" voltage ranges (voltage high/low unspecified) on input and output
      •  Logically combined voltage input/output differentials
      • (?) Specified voltage ranges may vary by point of reference, outside of manufacturers' actual data sheets
      • Principles and metrics of voltage, current, and IC fanout
    • Circuit power consumption
    • Clock frequencies
    • Circuit fanout
    • Contrast: CMOS (cf. MOSFET transistors)
  • Four microinstructions
    • ALU
    • BYTE
    • DISPATCH
    • JUMP
  • Memory, storage, display, and networking peripherals – applied to, if not furthermore in extensions of technologies available in the epoch of CADR's design
Quartus II
  • Developed by Altera
  • Focused primarily towards design, simulation, and application of FPGA platforms
  • May be used for design and simulation of non-FPGA platforms
  • Documentation: [Q2] Quartus II Handbook, PDF edition
  • Quartus II Web Edition
    • Available for free download and install
  • Application Use Cases may include
    • Block diagram definition
    • Waveform simulation
    • Device programming (e.g System on Chip devices, Altera FPGA programming)
    • Student lab exercises, at DeVry University Online
    • Modeling of Integrated Circuit (IC) logical profiles (e.g ideal 25S09 SEL-D FF)
    • Modeling of ICs as manufactured – historically and/or contemporarily – modeling in IC material profiles (e.g AM25S09 or low-power logical equivalent) as in material limitation of the ideal logical profile of any single IC element (e.g 25S09)
      • See also: Newton's contrast of geometry and mechanics, in the Principia
  • Quartus is a platform combining a significant number of tools for Electronic Design Automation (EDA)
  • Some individual tool components in Quartus are implemented as to support standardized hardware definition languages, including:
    • Verilog
    • VHDL
    • EDIF
  • Quartus Qsys system files
    • May be used to model, in each, an IC used in the original CADR schematic
      • Refer to: 
        • [Q2], p. 270, Creating Qsys Components
        • [Q2], p. 274, Creating Qsys Components in the Component Editor
      • Note that the components will be HDL-based, deriving from the Unlambda CADR Verilog Files
      • Some new Verilog files required
        • e.g to combine four ff_dsel modules into one (new) 25S09 module
          `include "ff_dsel.v"
          
          module m25S09(s,cp,d0a,d0b,d1a,d1b,d2a,d2b,d3a,d3b,q0,q1,q2,q3);
              input s,cp,d0a,d0b,d1a,d1b,d2a,d2b,d3a,d3b;
              output q0,q1,q2,q3;
          
              ff_dsel d0(q0,d0a,d0b,s,cp);
              ff_dsel d1(q1,d1a,d1b,s,cp);
              ff_dsel d2(q2,d2a,d2b,s,cp);
              ff_dsel d3(q3,d3a,d3b,s,cp);
          endmodule
          
        • must be determined per each individual IC defined in the schematics
    • Qsys IC component definitions may be combined within the Qsys System File editor
      • Refer to [Q2],, p. 195, Creating a Qsys system
Modeling CADR in Quartus II
  • Primary references
    • Public-Domain CADR Lisp Machine schematics, wiring, and design documents, published originally in MIT AI Memos
    • IC manufacturers' data sheets (archived)
  • Supporting resources
    • Verilog files for CADR, as published by Unlambda.com
      • Developer Notes:
        • Licensing not specified, assumed "Public domain"
        • Does not provide an exact model of the schematic – for instance, four Unlambda CADR Verilog ff_dsel (shared sel, clk pins) to each 25S09
        • CADR may be modeled, alternately, in other hardware defintion languages
          • NGSPICE defines a standard D flip-flop element, unbuffered. When defined in a module with buffer, then it might be compatible with Unlambda CADR Verilog ff_dsel and likewise, the original 25S09 IC logical profile.