Thursday, May 29, 2014

Modeling the LispM – Quartus II and CADR, an Outline

Ed. Note: This article should subsequently be updated for modeling of the CADR schematic, using Xilinux ISE Web Pack, and the Papilio FPGA platform -- ideally, then to develop an I2C bus as initial extension onto the original CADR design, such that the I2C bus could be operated via the GPIO headers on the Papilio platform, in communicating with one or more other devices on the same I2C backplane. See also: TI PRU Cape for the BeagleBone platform.


  • Lisp Machine
  • Developed at MIT (circa late 1970's, early 1980's)
  • Predecessor machine was CONS
  • Described in public domain (?) AI Memos originally published by the MIT AI Lab
    • Design
    • Schematics
    • Wiring/Pinouts
    • Peripherals incl. Chaosnet network interface
  • Designed in an era when integrated circuit (IC) technology was implemented primarily in applying techniques of transistor-transistor logic (TTL)
    • ICs composed of circuits of bijunction transistors, resistors, capacitors, packaged in multiple elements within individual integrated circuit modules (e.g four SEL-D FF elements to one 25S09 IC)
    • Standard (?) TTL logic/voltage bounds
      • high/lowmin/max voltage ranges on each of TTL circuit element input and output
      • "Nondeterministic" voltage ranges (voltage high/low unspecified) on input and output
      •  Logically combined voltage input/output differentials
      • (?) Specified voltage ranges may vary by point of reference, outside of manufacturers' actual data sheets
      • Principles and metrics of voltage, current, and IC fanout
    • Circuit power consumption
    • Clock frequencies
    • Circuit fanout
    • Contrast: CMOS (cf. MOSFET transistors)
  • Four microinstructions
    • ALU
    • BYTE
    • JUMP
  • Memory, storage, display, and networking peripherals – applied to, if not furthermore in extensions of technologies available in the epoch of CADR's design
Quartus II
  • Developed by Altera
  • Focused primarily towards design, simulation, and application of FPGA platforms
  • May be used for design and simulation of non-FPGA platforms
  • Documentation: [Q2] Quartus II Handbook, PDF edition
  • Quartus II Web Edition
    • Available for free download and install
  • Application Use Cases may include
    • Block diagram definition
    • Waveform simulation
    • Device programming (e.g System on Chip devices, Altera FPGA programming)
    • Student lab exercises, at DeVry University Online
    • Modeling of Integrated Circuit (IC) logical profiles (e.g ideal 25S09 SEL-D FF)
    • Modeling of ICs as manufactured – historically and/or contemporarily – modeling in IC material profiles (e.g AM25S09 or low-power logical equivalent) as in material limitation of the ideal logical profile of any single IC element (e.g 25S09)
      • See also: Newton's contrast of geometry and mechanics, in the Principia
  • Quartus is a platform combining a significant number of tools for Electronic Design Automation (EDA)
  • Some individual tool components in Quartus are implemented as to support standardized hardware definition languages, including:
    • Verilog
    • VHDL
    • EDIF
  • Quartus Qsys system files
    • May be used to model, in each, an IC used in the original CADR schematic
      • Refer to: 
        • [Q2], p. 270, Creating Qsys Components
        • [Q2], p. 274, Creating Qsys Components in the Component Editor
      • Note that the components will be HDL-based, deriving from the Unlambda CADR Verilog Files
      • Some new Verilog files required
        • e.g to combine four ff_dsel modules into one (new) 25S09 module
          `include "ff_dsel.v"
          module m25S09(s,cp,d0a,d0b,d1a,d1b,d2a,d2b,d3a,d3b,q0,q1,q2,q3);
              input s,cp,d0a,d0b,d1a,d1b,d2a,d2b,d3a,d3b;
              output q0,q1,q2,q3;
              ff_dsel d0(q0,d0a,d0b,s,cp);
              ff_dsel d1(q1,d1a,d1b,s,cp);
              ff_dsel d2(q2,d2a,d2b,s,cp);
              ff_dsel d3(q3,d3a,d3b,s,cp);
        • must be determined per each individual IC defined in the schematics
    • Qsys IC component definitions may be combined within the Qsys System File editor
      • Refer to [Q2],, p. 195, Creating a Qsys system
Modeling CADR in Quartus II
  • Primary references
    • Public-Domain CADR Lisp Machine schematics, wiring, and design documents, published originally in MIT AI Memos
    • IC manufacturers' data sheets (archived)
  • Supporting resources
    • Verilog files for CADR, as published by
      • Developer Notes:
        • Licensing not specified, assumed "Public domain"
        • Does not provide an exact model of the schematic – for instance, four Unlambda CADR Verilog ff_dsel (shared sel, clk pins) to each 25S09
        • CADR may be modeled, alternately, in other hardware defintion languages
          • NGSPICE defines a standard D flip-flop element, unbuffered. When defined in a module with buffer, then it might be compatible with Unlambda CADR Verilog ff_dsel and likewise, the original 25S09 IC logical profile.

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